IBM 25CPC710 - Manual (Page 4)

Page 4 of 8 Version 1.0 11/08/01
v Extended Addressing of PCI Memory
Ø System memory addressing range increased from 2GB to 4GB. The standard addressing
capability is 2GB; with the size defined by bits 24-31 of PCI local registers
PCILx_PSSIZE. The address extension is implemented by setting bit 27 of chip control
register CPC0_PGCHP. In this case, the FINE option for selection of less than1MB
granularity (enabled in CPC710-100+ dd2 in the memory write protection register
SDRAM0_MWPR) is not available.
PCI Interfaces:
v The PCI-64 Interface is no Longer 5 Volt Tolerant
Ø
The I/O drivers used on the CPC710 DD3.x PCI-64 interface no longer support 5V logic
levels – users must attach only 3.3V devices to the PCI-64 bus. This is a change from the
previous revision.
v PCI-32 Interface Now Supports External Arbiter Usage
Ø
The PCI-32 interface now allows use of an external PCI bus arbiter. A method similar to
that used for disabling the PCI-64 internal arbiter is used to for disabling the PCI-32
internal arbiter.
§
At power on, after activation of the POWERGOOD signal, the signal P_REQ2_ is
sampled. This initial sampling is done while PLL_RESET is active, and is
independent of activation of the PCI clock on the bus. If the signal level is 0, the
internal arbiter for the PCI-32 bus is disabled. Bit 16 of chip control register
CPC0_PGCHP can be read to determine the detected arbitration mode; a “0”
indicates the internal arbiter is in use, and a “1” indicates an external arbiter.
§
For the PCI-64 interface, the signal sampled after activation of the POWERGOOD
signal is G_REQ2_. This initial sampling is done while PLL_RESET is active, and
is independent of activation of the PCI clock on the bus. Bit 9 of chip control
register CPC0_PGCHP can be read to determine the detected arbitration mode; a
“0” indicates the internal arbiter is in use, and a “1” indicates an external arbiter.
Ø NOTE: Because the FLASH interface is present on the PCI-32 bus, configurations using
an external PCI bus arbiter must prevent any external PCI-32 transactions from interfering
or pre-empting FLASH transactions.
Power and PLL:
v New Supply Voltages
Ø
60x bus voltage level now 2.5V. To support the I/O interfaces on the PPC750CX/CXe (as
well as the PPC750L) the 60x bus interface logic is now 2.5V. This is a change from the
previous revision.
Ø
VDD (core logic) is also 2.5V.
Ø
OVDD (I/O logic) for SDRAM and PCI interfaces is 3.3V.
Ø
The AVDD (PLL) is 2.5V.
§ AVDD is the voltage supply pin to the analog circuits in the PLL. Noise on AVDD will
cause phase jitter at the output of the PLL. To provide isolation from the noisy
internal digital VDD signal, AVDD is brought to a package pin. If little noise is
expected at the board level, then AVDD can be connected directly to the digital VDD